Please refer to FIG. 1 which is a schematic block diagram illustrating an internal structure of a personal computer in communication with an external network. The personal computer includes a microprocessor 10, a north bridge chip 11, a south bridge chip 12, a memory 111 and a network interface card 121. The memory 111 is coupled to the north bridge chip 11. The network interface card 121 is coupled to the north bridge chip 11 via a peripheral component interconnect (PCI) bus. The network interface card 121 includes a media access controller (MAC) 1211 and a physical layer device (PHY) 1212. In some configurations, the MAC 1211 could be directly integrated into the south bridge chip 12. The PHY 1212 is used for connecting to an external network.
When tranceiving data packets, the MAC 1211 asserts an interrupt signal to the microprocessor 10 for interrupting hardware. The microprocessor 10 suspends the performing work to deal with an interrupt service routine (ISR) in the driver for the MAC 1211.
Conventionally, the MAC 1211 asserts an interrupt signal according to one of the following manners:    1. a packet-based manner, i.e. asserting a hardware interrupt signal whenever a data packet or a predetermined number of data packets to be transmitted;    2. a time-based manner, i.e. asserting a hardware interrupt signal periodically; or    3. a hybrid manner, i.e. combining the above packet- and time-based manners.
For the packet-based manner, the data packets can be timely picked up by the operating system, and the occupied memory resource is efficiently released. When the data packet throughput in the network is high, however, the frequently generated interrupt signals will result in that the operation resource of the microprocessor 10 is highly occupied by the network linking device so as to adversely affect the performance of the system.
On the other hand, for the time-based manner, the data packets can be processed to release the occupied memory resource without disturbing the microprocessor 10 too much. Once the data packet throughput is low, however, data packets must wait much longer to be transferred in response to the interruption, and the data packets cannot be efficiently transferred to the operating system.
For the hybrid manner, it is necessary to regulate the timing for asserting the interrupt signal to transfer data packets according to the data packet throughput. In practice, however, it is hard to control the timing for the MAC 1211 to assert the hardware interrupt signal since it is hard to predict the data packet throughput.
As described above, the assertion of the interrupt signal is either packet-based or time-based. For a situation that a data file includes a plurality of data packets and the data packets transmitted sequentially in response to the interrupt signal do not include the last packet of the data file, the microprocessor 10, although having been interrupted, will not notify the operating system to pick up the data packets. In stead, the data packets will be buffered in the memory. The occupied memory will not be released until the complete data file including the last packet is received. Meanwhile, the microprocessor 10 resumes the proceeding thread suspended due to the interruption. In other words, the interruption of the microprocessor 10, in spite of occupying the operation resource of the microprocessor 10, does not result in the release the occupied memory resource under this circumstance.
With the popularization of the broadband network, the data flow through the MAC 1211 increases a lot, and thus the interrupt frequency to the microprocessor 10 increases. The above-mentioned problem that the operation resource of the microprocessor 10 is unduly occupied is even serious. Especially for a server that cooperates with a plurality of terminals in a network system, several network interface cards (NICs) are required in the server to expand its bandwidth. If the network interface cards generate the interrupt signals in a manner as above, the performance of the server will be reduced due to frequent hardware interruption, and a hang-up situation may even occur.
Therefore, the purpose of the present invention is to contemplate how to assert the interrupt signal at proper timing.